HW2 - Q1 - ELEC 305

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Question 1) You are given a very simple single-channel VHDL debouncer circuit called "dut", and you are asked to test it by writing a VHDL testbench for it.
The sequence of inputs that should be given to the circuit is already determined as shown on the waveform diagram below. Your task is to replicate this.
The dut should get instantiated as dut_module on your testbench, and your testbench entity name has to be dut_tb.
Each time step in the waveform diagram is 5ns, i.e., the clock period is 10ns.

The server checks your testbench by connecting another testbench to it that reads (as inputs) the signals clk_tb_p, signal_in_tb_p and signal_out_tb_p that come out of your testbench.
Therefore, unlike the other testbenches we build, you will need to connect your internal signals to output Ports in your entity declaration.
See the descriptive diagram below for more info:



Your dut_tb VHDL testbench replicating the waveform diagram above:



         

Links to other questions in HW 2