Q1 - HW1 - ELEC 305

HW1 - Q1 - ELEC 305

Please enter your username and password below before submitting.

ELEC 305 username:
ELEC 305 password:

Question 1) Describe a very simple VHDL circuit that takes a 1-bit signal called A as input,
and just connects that to a 1-bit output signal named B. Use the std_logic data type.

- Signal/port names must be *exactly* the same as in the question, and entity name must be hw1_q1.
- You can check the server testbench for this question at content/hw1_q1_tb.vhdl.

Your VHDL:

...

Links to other questions in HW 1

- Question 2
- Question 3
- Question 4
- Question 5