Q4 - HW1 - ELEC 305

HW1 - Q4 - ELEC 305

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Question 4) Describe a simple VHDL circuit that takes a 2-bit vector called A as input,
and drives a 3-bit output named B with the truth table given below. Use the std_logic_vector data type.

A(0)	A(1)	B(0)	B(1)	B(2)
0	0	0	0	0
0	1	0	1	1
1	0	0	1	1
1	1	1	1	0

- Signal/port names must be *exactly* the same as in the question, and entity name must be hw1_q4.
- You can check the server testbench for this question at content/hw1_q4_tb.vhdl.

Your VHDL:

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Links to other questions in HW1

- Question 1
- Question 2
- Question 3
- Question 5