Q3 - HW1 - ELEC 305

HW1 - Q3 - ELEC 305

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Question 3) Describe a simple VHDL circuit that takes two 1-bit signals called A and B as input,
and drives a 1-bit output named C with the logical XOR of A and B. Use the std_logic data type.

- Signal/port names must be *exactly* the same as in the question, and entity name must be hw1_q3.
- You can check the server testbench for this question at content/hw1_q3_tb.vhdl.

Your VHDL:

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Links to other questions in HW1

- Question 1
- Question 2
- Question 4
- Question 5