Q5 - HW1 - ELEC 305

HW1 - Q5 - ELEC 305

Please enter your username and password below before submitting.

ELEC 305 username:
ELEC 305 password:

Question 5) Describe a VHDL circuit that takes a 1-bit signal called A as well as
a clock signal called clk as input, and drives a 2-bit vector named leds (each bit drives an LED).
The LEDs should toggle at every rising edge of clk, and they should be conditional to A,
i.e., when A=0, leds(0) should be blinking, and when A=1, leds(1) should be blinking.
Use the std_logic and std_logic_vector data types.

- Signal/port names must be *exactly* the same as in the question, and entity name must be hw1_q5.
- You can check the server testbench for this question at content/hw1_q5_tb.vhdl.

Your VHDL:

...

Links to other questions in HW1

- Question 1
- Question 2
- Question 3
- Question 4