Q2 - HW1 - ELEC 305

HW1 - Q2 - ELEC 305

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Question 2) Describe a very simple VHDL circuit that takes a 1-bit signal called A as input,
and just connects the logical inverse of that to a 1-bit output signal named B. Use the std_logic data type.
So the same circuit as Question 1, but this time make B equal to the 1-bit inverse of A (logical not).

- Signal/port names must be *exactly* the same as in the question, and entity name must be hw1_q2.
- You can check the server testbench for this question at content/hw1_q2_tb.vhdl.

Your VHDL:

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Links to other questions in HW1

- Question 1
- Question 3
- Question 4
- Question 5